Array substrate for reducing parasitic capacitance between adjacent wires, display panel, and display device
Abstract:
An array substrate carrying a display area and a camera area surrounded by the display area provides connections to both areas free of electrical interference. The camera area includes a transparent area and a routing area surrounding the transparent area. The array substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes first wires and first capacitance compensation patterns. The second conductive layer includes second wires. Each first capacitance compensation pattern is between adjacent first wires. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps with a projection of at least one second wire. A display panel and a display device are also disclosed.
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