Invention Grant
- Patent Title: Array substrate for reducing parasitic capacitance between adjacent wires, display panel, and display device
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Application No.: US16857979Application Date: 2020-04-24
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Publication No.: US11226528B2Publication Date: 2022-01-18
- Inventor: Shiang-Ruei Ouyang , Wei-Cheng Chen
- Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
- Applicant Address: TW New Taipei
- Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
- Current Assignee Address: TW New Taipei
- Agency: ScienBiziP, P.C.
- Priority: CN202010028531.7 20200111
- Main IPC: G02F1/1333
- IPC: G02F1/1333 ; G02F1/1362 ; G03B30/00 ; G06F1/16 ; H01L23/522 ; H01L27/12 ; G02F1/136 ; G02F1/1335 ; G02F1/13357

Abstract:
An array substrate carrying a display area and a camera area surrounded by the display area provides connections to both areas free of electrical interference. The camera area includes a transparent area and a routing area surrounding the transparent area. The array substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes first wires and first capacitance compensation patterns. The second conductive layer includes second wires. Each first capacitance compensation pattern is between adjacent first wires. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps with a projection of at least one second wire. A display panel and a display device are also disclosed.
Public/Granted literature
- US20210215983A1 ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE Public/Granted day:2021-07-15
Information query
IPC分类: