Invention Grant
- Patent Title: Resistive random-access memory and architecture with select and control transistors
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Application No.: US16943594Application Date: 2020-07-30
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Publication No.: US11227654B2Publication Date: 2022-01-18
- Inventor: Hagop Nazarian
- Applicant: CROSSBAR, INC.
- Applicant Address: US CA Santa Clara
- Assignee: CROSSBAR, INC.
- Current Assignee: CROSSBAR, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Wegman Hessler
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00

Abstract:
A semiconductor device includes memory devices respectively comprising a selector transistor in series with a control transistor and a memory cell, wherein the control transistor is connected to the memory cell. Control lines of the semiconductor device extend along a first direction, and a first control line is connected to a first memory device control transistor and a second memory device control transistor. Word lines extend in the first direction, and a first word line is connected to a first memory device selector transistor and a second memory device selector transistor. Bitlines extend in a second direction, with a first bitline connected to a first memory device memory cell and a second bitline is connected to a second memory device memory cell. Source lines extend in the second direction, and a first source line is connected to the first memory device selector transistor and the second memory device selector transistor.
Public/Granted literature
- US20210035636A1 RESISTIVE RANDOM-ACCESS MEMORY AND ARCHITECTURE WITH SELECT AND CONTROL TRANSISTORS Public/Granted day:2021-02-04
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