Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US16745991Application Date: 2020-01-17
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Publication No.: US11227795B2Publication Date: 2022-01-18
- Inventor: Ting-Chen Tseng , Sih-Hao Liao , Po-Han Wang , Yu-Hsiang Hu , Hung-Jui Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/22 ; H01L21/311

Abstract:
In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.
Public/Granted literature
- US20210225699A1 Integrated Circuit Package and Method Public/Granted day:2021-07-22
Information query
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