A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.