Invention Grant
- Patent Title: Semiconductor structure and fabrication method
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Application No.: US16452114Application Date: 2019-06-25
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Publication No.: US11227803B2Publication Date: 2022-01-18
- Inventor: Jian Qiang Liu , Chao Tian , Zi Rui Liu , Ching Yun Chang , Ai Ji Wang
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai; CN Beijing
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation,Semiconductor Manufacturing International (Beijing) Corporation
- Current Assignee Address: CN Shanghai; CN Beijing
- Agency: Anova Law Group, PLLC
- Priority: CN201810665699.1 20180625
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L21/28 ; H01L29/49 ; H01L27/092

Abstract:
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having an opening and forming a first gate layer in the opening. The first gate layer closes a top of the opening and includes a void. The method also includes forming a second gate layer on the first gate layer. An atomic radius of a material of the second gate layer is smaller than gaps among the atoms of the material of the first gate layer. Further, the method includes performing a thermal annealing process to cause atoms of the material of the second layer to pass through the first gate layer to fill the void.
Public/Granted literature
- US20190393093A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD Public/Granted day:2019-12-26
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