Invention Grant
- Patent Title: Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof
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Application No.: US16819709Application Date: 2020-03-16
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Publication No.: US11227814B2Publication Date: 2022-01-18
- Inventor: Wu-Der Yang , Chun-Huang Yu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds and Lowe, P.C.
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/48 ; H01L21/00 ; H01L21/44 ; B23K31/02 ; H01L23/495 ; H01L23/544 ; H01L21/56 ; H01L23/498 ; H01L23/00 ; H01L25/00

Abstract:
The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.
Public/Granted literature
Information query
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