Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US16868111Application Date: 2020-05-06
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Publication No.: US11227837B2Publication Date: 2022-01-18
- Inventor: Chen-Hua Yu , Jen-Fu Liu , Ming Hung Tseng , Tsung-Hsien Chiang , Yen-Liang Lin , Tzu-Sung Huang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/29 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L25/00 ; H01L25/10

Abstract:
In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.
Public/Granted literature
- US20210193582A1 Integrated Circuit Package and Method Public/Granted day:2021-06-24
Information query
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