Invention Grant
- Patent Title: Alignment device, semiconductor wafer processing device, and alignment method
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Application No.: US16236766Application Date: 2018-12-31
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Publication No.: US11232962B2Publication Date: 2022-01-25
- Inventor: Hiroki Watanabe , Tetsuya Sakai , Hiroshi Kikai
- Applicant: HIRATA CORPORATION
- Applicant Address: JP Kumamoto
- Assignee: HIRATA CORPORATION
- Current Assignee: HIRATA CORPORATION
- Current Assignee Address: JP Kumamoto
- Agency: Paratus Law Group, PLLC
- Priority: JPJP2018-122933 20180628
- Main IPC: H01L21/67
- IPC: H01L21/67 ; H01L21/68 ; H01L21/687
Abstract:
An alignment device which aligns notch portions of wafers includes mounting tables that hold the wafers, movement units that move the mounting tables, notch portion detection units that detect a circumferential positions of the notch portion, and a controller that controls positions of the mounting tables by the movement units. The mounting tables includes a mounting table main body portion and a pad member attached to an opening in the mounting table main body portion to hold the wafers. The pad member includes the main body portion that is attached to the opening and has a through hole in a center portion thereof, the first annular portion on an end side of the pad member to abut against wafers, and the first collar portion that is integrally provided with the first annular portion and the main body portion and extends toward outside of the main body portion.
Public/Granted literature
- US20200006103A1 ALIGNMENT DEVICE, SEMICONDUCTOR WAFER PROCESSING DEVICE, AND ALIGNMENT METHOD Public/Granted day:2020-01-02
Information query
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