Invention Grant
- Patent Title: Semiconductor package with inner lead pattern group and method for manufacturing the semiconductor package
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Application No.: US16503897Application Date: 2019-07-05
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Publication No.: US11233000B2Publication Date: 2022-01-25
- Inventor: Jae Sik Choi , Do Young Kim , Jin Won Jeong , Hye Ji Lee
- Applicant: MagnaChip Semiconductor, Ltd.
- Applicant Address: KR Cheongju-si
- Assignee: MagnaChip Semiconductor, Ltd.
- Current Assignee: MagnaChip Semiconductor, Ltd.
- Current Assignee Address: KR Cheongju-si
- Agency: NSIP Law
- Priority: KR10-2019-0025437 20190305
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/528 ; H01L27/12

Abstract:
A semiconductor package includes a first metal interconnection disposed in a semiconductor chip, a first bump group configured to be connected to the first metal interconnection, a first inner lead pattern group configured to be connected to the first bump group, a second metal interconnection disposed in the semiconductor chip, a second bump group configured to be connected to the second metal interconnection; and a second inner lead pattern group configured to be connected to the second bump group, wherein a density of the first metal interconnection is greater than a density of the second metal interconnection, such that a first pitch of the first lead pattern group is greater than a second pitch of the second lead pattern group.
Public/Granted literature
Information query
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