Invention Grant
- Patent Title: Data erasure in memory sub-systems
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Application No.: US16824335Application Date: 2020-03-19
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Publication No.: US11237755B2Publication Date: 2022-02-01
- Inventor: Kevin R Brandt , Thomas Cougar Van Eaton
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; H04L9/08

Abstract:
Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
Public/Granted literature
- US20200218467A1 DATA ERASURE IN MEMORY SUB-SYSTEMS Public/Granted day:2020-07-09
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