Invention Grant
- Patent Title: Error correction using hierarchical decoders
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Application No.: US16834198Application Date: 2020-03-30
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Publication No.: US11237901B2Publication Date: 2022-02-01
- Inventor: Paolo Amato , Marco Sforzin
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/10 ; H03M13/29 ; H03M13/11

Abstract:
Apparatuses and methods related to correcting errors can include using FD decoders and AD decoders. Correcting errors can include receiving input data from the memory array, performing a plurality of operations associated with an error detection on the input data, and providing, based on processing the input data, output data, a validation flag, and a plurality of parity bits to a second decoder hosted by a controller coupled to the memory device.
Public/Granted literature
- US20200226020A1 ERROR CORRECTION USING HIERARCHICAL DECODERS Public/Granted day:2020-07-16
Information query
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