Invention Grant
- Patent Title: Apparatuses and methods for compute components formed over an array of memory cells
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Application No.: US17107463Application Date: 2020-11-30
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Publication No.: US11238914B2Publication Date: 2022-02-01
- Inventor: Jason T. Zawodny
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/402 ; G11C11/406 ; G11C11/403 ; G11C5/02 ; G11C7/10 ; G11C11/407

Abstract:
The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.
Public/Granted literature
- US20210110858A1 APPARATUSES AND METHODS FOR COMPUTE COMPONENTS FORMED OVER AN ARRAY OF MEMORY CELLS Public/Granted day:2021-04-15
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