Invention Grant
- Patent Title: Topside-cooled semiconductor package with molded standoff
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Application No.: US16906617Application Date: 2020-06-19
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Publication No.: US11239127B2Publication Date: 2022-02-01
- Inventor: Edward Myers , Liu Chen , Chee Chiew Chong , Wee Aun Jason Lim , Wee Boon Tay
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Harrity & Harrity, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/31 ; H01L23/36 ; H01L23/00 ; H01L21/56 ; H01L23/498

Abstract:
A molded semiconductor package arrangement may comprise a die pad configured to support a semiconductor; a set of leads; and a mold structure that is formed to enclose the semiconductor and the die pad within the mold structure. The set of leads and the die pad may be formed from a same piece of conductive material. An electrical contact plane of the set of leads may be offset from a bottom surface of the die pad. The mold structure may include a molded standoff that is beneath the die pad. A bottom surface of the molded standoff may extend below the electrical contact plane of the set of leads by a threshold distance that corresponds to a thickness of the molded standoff.
Public/Granted literature
- US20210398867A1 TOPSIDE-COOLED SEMICONDUCTOR PACKAGE WITH MOLDED STANDOFF Public/Granted day:2021-12-23
Information query
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