Invention Grant
- Patent Title: Selective molding for integrated circuit
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Application No.: US16597915Application Date: 2019-10-10
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Publication No.: US11239130B2Publication Date: 2022-02-01
- Inventor: Dolores Babaran Milo , Floro Lopez Camenforte, III , Joe Anne Feive Carbonell Lopez
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L23/495 ; H01L21/56 ; H01L25/00

Abstract:
A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.
Public/Granted literature
- US20210111086A1 SELECTIVE MOLDING FOR INTEGRATED CIRCUIT Public/Granted day:2021-04-15
Information query
IPC分类: