Invention Grant
- Patent Title: Package structure and package-on-package structure
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Application No.: US16995779Application Date: 2020-08-17
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Publication No.: US11239157B2Publication Date: 2022-02-01
- Inventor: Chuei-Tang Wang , Chung-Hao Tsai , Chen-Hua Yu , Wei-Ting Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/00 ; H01L49/02 ; H01L21/768 ; H01L23/532 ; H01L21/56

Abstract:
A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.
Public/Granted literature
- US20200381357A1 PACKAGE STRUCTURE AND PACKAGE-ON-PACKAGE STRUCTURE Public/Granted day:2020-12-03
Information query
IPC分类: