Invention Grant
- Patent Title: Package stacking using chip to wafer bonding
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Application No.: US15774906Application Date: 2015-12-26
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Publication No.: US11239199B2Publication Date: 2022-02-01
- Inventor: Georg Seidemann , Klaus Reingruber , Christian Geissler , Sven Albers , Andreas Wolter , Marc Dittes , Richard Patten
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/000394 WO 20151226
- International Announcement: WO2017/111836 WO 20170629
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L25/065 ; H01L23/00 ; H01L25/00 ; H01L23/498 ; H01L21/48 ; H01L23/31 ; H01L23/538 ; H01L21/56

Abstract:
Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
Public/Granted literature
- US20180331070A1 PACKAGE STACKING USING CHIP TO WAFER BONDING Public/Granted day:2018-11-15
Information query
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