Invention Grant
- Patent Title: Forksheet transistor architectures
-
Application No.: US16827566Application Date: 2020-03-23
-
Publication No.: US11239236B2Publication Date: 2022-02-01
- Inventor: Aaron D. Lilak , Rishabh Mehandru , Ehren Mannebach , Patrick Morrow , Willy Rachmady
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L23/528 ; H01L29/10

Abstract:
Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a first transistor strata. The first transistor strata comprises a first backbone, a first transistor adjacent to a first edge of the first backbone, and a second transistor adjacent to a second edge of the first backbone. In an embodiment, the semiconductor device further comprises a second transistor strata over the first transistor strata. The second transistor strata comprises a second backbone, a third transistor adjacent to a first edge of the second backbone, and a fourth transistor adjacent to a second edge of the second backbone.
Public/Granted literature
- US20210296315A1 FORKSHEET TRANSISTOR ARCHITECTURES Public/Granted day:2021-09-23
Information query
IPC分类: