A MOSFET that has a drain region and a source region on an upper surface of a semiconductor substrate and a gate electrode that is formed on the semiconductor substrate, and an element separation insulating film that includes an opening portion which exposes an active region, on the semiconductor substrate, are formed. At this point, a gate leading-out interconnection that overlaps the element separation insulating film when viewed from above, and that is integrally combined with the gate electrode is formed in a position where the gate leading-out interconnection does not extend over a distance between both the drain region and the source region when viewed from above, on a region that is exposed from the gate electrode.