Invention Grant
- Patent Title: Classifier circuits with graphene transistors
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Application No.: US16706004Application Date: 2019-12-06
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Publication No.: US11239320B2Publication Date: 2022-02-01
- Inventor: Wenjuan Zhu , Jialun Liu , Hojoon Ryu
- Applicant: The Board of Trustees of the University of Illinois
- Applicant Address: US IL Urbana
- Assignee: The Board of Trustees of the University of Illinois
- Current Assignee: The Board of Trustees of the University of Illinois
- Current Assignee Address: US IL Urbana
- Agency: Greer, Burns & Crain, Ltd.
- Agent Steven P. Fallon
- Main IPC: H01L29/16
- IPC: H01L29/16 ; H01L29/786 ; H01L29/66 ; H01L29/51 ; H01L29/78

Abstract:
A classifier circuit includes an array of dual gate graphene transistors, each of the transistors having a source, a top gate receiving one of an input voltage to be evaluated or a reference voltage, a bottom or embedded gate receiving the other of the input voltage or reference voltage and a drain, the source and drain contacting a graphene channel One of the source and the drain is connected to a voltage source. A common output combines output current of a plurality of the dual gate graphene transistors, which current varies in response to the difference between the input voltage and the reference voltage. A method for forming a classifier transistor with high remanent polarization forms dielectric with ferroelectric capability on a low resistivity substrate. A non-ferroelectric oxide layer is formed on the dielectric. A window is opened, and a graphene channel is formed in the window.
Information query
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