Invention Grant
- Patent Title: Semiconductor devices having stressed active regions therein and methods of forming same
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Application No.: US16412463Application Date: 2019-05-15
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Publication No.: US11239362B2Publication Date: 2022-02-01
- Inventor: Hoon-Sung Choi
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Myers Bigel, P.A.
- Priority: KR10-2018-0071254 20180621
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/02 ; H01L29/06 ; H01L29/165 ; H01L29/08 ; H01L21/762

Abstract:
A method of fabricating a semiconductor device includes providing a substrate including a semiconductor material having a first lattice constant and then patterning the substrate to form a first semiconductor pattern extending in a first direction. A second semiconductor pattern is also formed on and in contact with the first semiconductor pattern. The second semiconductor pattern extends in the first direction and has a second lattice constant that is sufficiently greater than the first lattice constant so that lattice stress is present at an interface between the first semiconductor pattern and the second semiconductor pattern. The second semiconductor pattern is further patterned to define a sidewall of the second semiconductor pattern that extends in a second direction intersecting the first direction. A gate electrode is formed, which extends in the first direction on the second semiconductor pattern.
Public/Granted literature
- US20190393348A1 SEMICONDUCTOR DEVICES HAVING STRESSED ACTIVE REGIONS THEREIN AND METHODS OF FORMING SAME Public/Granted day:2019-12-26
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