A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.