Invention Grant
- Patent Title: Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
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Application No.: US16655850Application Date: 2019-10-17
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Publication No.: US11239860B2Publication Date: 2022-02-01
- Inventor: Shrinivas Kudekar , Thomas Joseph Richardson
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Qualcomm IP Dept.
- Agent James Hunt Yancey, Jr.
- Main IPC: H03M13/11
- IPC: H03M13/11 ; H03M13/00 ; H03M13/03 ; H04L1/18 ; H04L1/00

Abstract:
Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.
Public/Granted literature
- US20200052817A1 METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES Public/Granted day:2020-02-13
Information query
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