Invention Grant
- Patent Title: Overlay measurement structures with variable width/pitch for measuring overlay errors
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Application No.: US17063184Application Date: 2020-10-05
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Publication No.: US11243475B2Publication Date: 2022-02-08
- Inventor: Yen-Liang Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McDermott Will & Emery LLP
- Main IPC: G03F7/20
- IPC: G03F7/20 ; G01B11/27 ; G03F9/00

Abstract:
An overlay error measurement structure includes a lower-layer pattern disposed over a substrate, and an upper-layer pattern disposed over the lower-layer pattern and at least partially overlapping with the lower-layer pattern. The lower-layer pattern includes a plurality of first sub-patterns extending in a first direction and being arranged in a second direction crossing the first direction. The upper-layer pattern includes a plurality of second sub-patterns extending in the first direction and being arranged in the second direction. At least one of a pattern pitch and a pattern width of at least one of at least a part of the first sub-patterns and at least a part of the second sub-patterns varies along the second direction.
Public/Granted literature
- US20210018851A1 Overlay measurement structures and method of overlay errors Public/Granted day:2021-01-21
Information query
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