A series circuit and a computing device includes a power supply terminal, a ground terminal and a first connection line for separately connecting a first predetermined number of chips of the plurality of chips in series. A communication line is connected between adjacent chips of the first predetermined number of chips. A portion of the communication line is connected to a target connection point, which is disposed on the first connection line and adapted to the adjacent chips, via a second connection line, and the voltage at the target connection point is greater than or equal to the minimum voltage required for communication between the adjacent chips.