A memory system includes at least one memory device, including plural planes, each capable of storing data; and a controller coupled with the at least one memory device via plural channels and plural ways and suitable for transmitting data to the at least one memory device for a read operation or a write operation in response to a transmission order. The plural planes can include plural blocks respectively. The plural blocks can include multi-level cells respectively. The controller can include a mapping circuitry for determining the transmission order of the data based on a first order of the plural channels, a second order of the plural planes, a third order of the plural ways and a fourth order of bits stored in the multi-level cells.