Invention Grant
- Patent Title: Flexible instruction set disabling
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Application No.: US16582701Application Date: 2019-09-25
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Publication No.: US11243766B2Publication Date: 2022-02-08
- Inventor: Rodrigo Branco
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F1/3293 ; G06F9/30 ; G06F9/32 ; G06F9/52
Abstract:
There is disclosed in one example a microprocessor, including: a decoder; an execution unit; an instruction set flag vector; and logic to decode an instruction, read a binary disable flag for the instruction within the instruction set flag vector, and execute the instruction within the execution unit only if the disable flag for the instruction is not set.
Public/Granted literature
- US20200019403A1 FLEXIBLE INSTRUCTION SET DISABLING Public/Granted day:2020-01-16
Information query
