Invention Grant
- Patent Title: Framing protocol supporting low-latency serial interface in an emulation system
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Application No.: US16217465Application Date: 2018-12-12
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Publication No.: US11243856B1Publication Date: 2022-02-08
- Inventor: Yuhei Hayashi , Mitchell G. Poplack
- Applicant: CADENCE DESIGN SYSTEMS, INC.
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Foley & Lardner LLP
- Main IPC: G06F11/22
- IPC: G06F11/22 ; G06F11/273 ; G06F30/331 ; G06F9/455 ; H04L29/08

Abstract:
Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such that the switching ASIC may stop routing data through the SerDes interface during the gap cycles. The start-of-packet molecule may include a start-of-packet word, a status word, cyclic redundancy check word, and an idle word. The end-of-packet molecule may include an end-of-packet word, a status word, a cyclic redundancy check word, and an idle word.
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