A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders respectively connected to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and wherein each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected, The memory device may include a sense amplifier circuit including sense amplifiers connected to the bitlines, and a logic circuit configured to determine a failure of at least one of the memory cell array and the wordline driving circuit.