Invention Grant
- Patent Title: Single page read level tracking by bit error rate analysis
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Application No.: US16364347Application Date: 2019-03-26
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Publication No.: US11244732B2Publication Date: 2022-02-08
- Inventor: Eran Sharon , Alex Bazarsky , Idan Alrod
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Dickinson Wright PLLC
- Agent Steven Hurles
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C29/02 ; G11C29/50 ; G11C11/56 ; G06F11/07 ; G11C7/14 ; G11C16/28

Abstract:
A method for calibrating read threshold voltages includes receiving, from at least one memory die, a number of page bits corresponding to a number of read operations performed on a page associated with the at least one memory die. The method further includes determining voltage bins for each bit of the number of page bits. The method further includes determining, for each voltage bin, a bit error rate. The method further includes adjusting read threshold voltages associated with the at least one memory die using the bite error rate for each voltage bin.
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