A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.