A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.