The present application discloses a display apparatus including a solution-on-chip (SOC) comprising a first input port receiving video data, a second input port configured to receive image data in a first resolution, and a central-processing unit comprising a frame-cut block integrated with an image processor to divide a frame of image data in the first resolution to 4 parts of the frame in a second resolution in a serial order. The display apparatus further includes a FPGA configured to write, read, and process respective one of the 4 parts of the frame in the serial order sent from the SOC to reconstruct a frame of image data in the first resolution. Furthermore, the display apparatus includes a TCON configured to receive the frame of the image data in the first resolution reconstructed by the FPGA and a display panel driven by the TCON to display the frame of image data.