Invention Grant
- Patent Title: Scrambling using different scrambling seeds for defect reduction and improved programming efficiency
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Application No.: US16880845Application Date: 2020-05-21
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Publication No.: US11250913B2Publication Date: 2022-02-15
- Inventor: Sudipta Dutta , Amiya Banerjee
- Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Arent Fox LLP
- Main IPC: G11C16/10
- IPC: G11C16/10 ; G11C16/08 ; G06F3/06 ; G11C11/56 ; G11C16/04

Abstract:
Aspects of a storage device including a memory and a controller are provided which allow for efficient programming of cells on word lines using different scrambling seeds. The controller attempts to program cells of the memory by applying data scrambled using a first scrambling seed to the word line. If this attempt to program fails, the controller scrambles the data using a second, different scrambling seed and attempts to program the cells by applying the re-scrambled data to the word line. If this re-attempt also fails, the word line is listed. Then when the controller receives other data, the controller performs a final programming attempt with the other data scrambled using the second scrambling seed. If this further attempt fails, the controller identifies the block including the failed word line as a GBB. Thus, fewer GBBs may be incorrectly identified, reducing DPPM and improving memory yield of the storage device.
Public/Granted literature
- US20210366549A1 Scrambling Using Different Scrambling Seeds for Defect Reduction and Improved Programming Efficiency Public/Granted day:2021-11-25
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