Invention Grant
- Patent Title: Selective deposition of barrier layer
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Application No.: US16837968Application Date: 2020-04-01
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Publication No.: US11251073B2Publication Date: 2022-02-15
- Inventor: Hsin-Yen Huang , Hai-Ching Chen , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/786
- IPC: H01L21/786 ; H01L21/02 ; H01L21/768 ; H01L21/311 ; H01L21/306

Abstract:
Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
Public/Granted literature
- US20210313223A1 Selective Deposition of Barrier Layer Public/Granted day:2021-10-07
Information query
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