Invention Grant
- Patent Title: SOI device structure for robust isolation
-
Application No.: US16886386Application Date: 2020-05-28
-
Publication No.: US11257902B2Publication Date: 2022-02-22
- Inventor: Lin-Chen Lu , Gulbagh Singh , Tsung-Han Tsai , Po-Jen Wang
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: Foley & Lardner LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762 ; H01L29/10 ; H01L23/66

Abstract:
This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.
Public/Granted literature
- US20210376070A1 NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION Public/Granted day:2021-12-02
Information query
IPC分类: