Invention Grant
- Patent Title: Current mirror arrangements with semi-cascoding
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Application No.: US16861915Application Date: 2020-04-29
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Publication No.: US11262782B2Publication Date: 2022-03-01
- Inventor: Devrim Aksin , Omid Foroudi
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Patent Capital Group
- Main IPC: G05F3/26
- IPC: G05F3/26 ; H03F3/14 ; H03M1/12 ; H03F3/345

Abstract:
An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.
Public/Granted literature
- US20210341959A1 CURRENT MIRROR ARRANGEMENTS WITH SEMI-CASCODING Public/Granted day:2021-11-04
Information query
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