Invention Grant
- Patent Title: Method of epitaxy and semiconductor device
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Application No.: US16460745Application Date: 2019-07-02
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Publication No.: US11264237B2Publication Date: 2022-03-01
- Inventor: Chih-Yun Chin , Tzu-Hsiang Hsu , Yen-Ru Lee , Chii-Horng Li
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/02 ; H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L21/768
Abstract:
A transistor is provided including a source-drain region, the source-drain region including a first layer wherein a first average silicon content is between about 80% and 100%, a second layer wherein a second average silicon content is between zero and about 90%, the second average silicon content being smaller than the first average silicon content by at least 7%, and the second layer disposed on and adjacent the first layer, a third layer wherein a third average silicon content is between about 80% and 100%, and a fourth layer wherein a fourth average silicon content is between zero and about 90%, the fourth average silicon content being smaller than the third average silicon content by at least 7%, and the fourth layer disposed on and adjacent the third layer.
Information query
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