Invention Grant
- Patent Title: Semiconductor device with spacers for self aligned vias
-
Application No.: US16669917Application Date: 2019-10-31
-
Publication No.: US11264277B2Publication Date: 2022-03-01
- Inventor: Pokuan Ho , Hsin-Ping Chen , Chia-Tien Wu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
- Current Assignee Address: TW Hsin-Chu
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522
Abstract:
A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.
Public/Granted literature
- US20210134672A1 SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS Public/Granted day:2021-05-06
Information query
IPC分类:
