Invention Grant
- Patent Title: System and method to enhance reliability in connection with arrangements including circuits
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Application No.: US16821926Application Date: 2020-03-17
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Publication No.: US11264301B2Publication Date: 2022-03-01
- Inventor: Lee Kong Yu , Sungjun Im , Chun Sean Lau , Yoong Tatt Chin , Paramjeet Singh Gill , Weng-Hong Teh
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: H01L23/367
- IPC: H01L23/367 ; H01L23/31 ; H01L23/373 ; H01L21/66 ; H01L21/56 ; H01L21/48 ; H01L23/00
Abstract:
A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
Public/Granted literature
- US20200219787A1 System and Method to Enhance Solder Joint Reliability Public/Granted day:2020-07-09
Information query
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