Invention Grant
- Patent Title: Isolation trenches augmented with a trap-rich layer
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Application No.: US16953897Application Date: 2020-11-20
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Publication No.: US11264457B1Publication Date: 2022-03-01
- Inventor: Mark Levy , Siva P. Adusumilli , Steven M. Shank , Alvin J. Joseph , Anthony K. Stamper
- Applicant: GLOBALFOUNDRIES U.S. Inc.
- Applicant Address: US CA Santa Clara
- Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee: GLOBALFOUNDRIES U.S. Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Thompson Hine LLP
- Agent Francois Pagette
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/763 ; H01L27/06 ; H01L21/762

Abstract:
Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.
Information query
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