Invention Grant
- Patent Title: Method for manufacturing semiconductor device
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Application No.: US16444942Application Date: 2019-06-18
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Publication No.: US11264473B2Publication Date: 2022-03-01
- Inventor: Toshiya Saitoh
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JPJP2018-119466 20180625
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763 ; H01L29/423 ; H01L29/51 ; H01L21/027 ; H01L21/311 ; H01L21/3213 ; H01L21/02 ; H01L21/28
Abstract:
A method of manufacturing a split-gate type nonvolatile memory improving reliability and manufacturing yield. In a method of manufacturing a split-gate type nonvolatile memory in which a memory gate electrode is formed prior to a control gate electrode, a protective film is formed to cover the gate insulating film exposed between control gate electrodes before unnecessary control gate electrodes are removed.
Public/Granted literature
- US20190393317A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2019-12-26
Information query
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