Invention Grant
- Patent Title: High performance phase locked loop
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Application No.: US16813526Application Date: 2020-03-09
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Publication No.: US11265140B2Publication Date: 2022-03-01
- Inventor: Armin Tajalli
- Applicant: Kandou Labs SA
- Applicant Address: CH Lausanne
- Assignee: Kandou Labs SA
- Current Assignee: Kandou Labs SA
- Current Assignee Address: CH Lausanne
- Agency: Invention Mine LLC
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L7/033 ; H03K3/356 ; H02M3/07 ; H03K5/26 ; H03L7/099 ; H03L7/00 ; H03L7/10

Abstract:
Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
Public/Granted literature
- US20200213075A1 HIGH PERFORMANCE PHASE LOCKED LOOP Public/Granted day:2020-07-02
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