Invention Grant
- Patent Title: Memory controller, memory system, information processing system, and memory control method
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Application No.: US16629615Application Date: 2018-04-03
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Publication No.: US11269546B2Publication Date: 2022-03-08
- Inventor: Kenichi Nakanishi
- Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: Chip Law Group
- Priority: JPJP2017-138782 20170718
- International Application: PCT/JP2018/014241 WO 20180403
- International Announcement: WO2019/017017 WO 20190124
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F3/06 ; G06F12/02

Abstract:
Efficient wear leveling processing is performed in a memory in which the number of times of writing may vary for each of pages that are access units. An address conversion unit performs address conversion between a logical address of a host command and a physical address of the memory for each of management units, the management units each including a plurality of access units of the memory. A write amount measurement unit measures a write amount for each of the access units in each of the management units. The averaging processing unit selects a target management unit from the management units on the basis of the write amount measured by the write amount measurement unit and changes physical address allocation in the address conversion of the target management unit. Then, the averaging processing unit performs processing of averaging write amounts of the access units in the target management unit.
Public/Granted literature
- US20210081136A1 MEMORY CONTROLLER, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD Public/Granted day:2021-03-18
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