Invention Grant
- Patent Title: System and method for executing a number of NOP instructions after a repeated instruction
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Application No.: US17303746Application Date: 2021-06-07
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Publication No.: US11269633B1Publication Date: 2022-03-08
- Inventor: Kevin Bruce Traylor
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Agent Daniel D. Hill
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38

Abstract:
A method is provided for executing instructions in a pipelined processor. The method includes receiving a plurality of instructions in the pipelined processor. A first instruction of the plurality of instructions has a first bit field for holding a value for indicating how many times execution of the first instruction is repeated. Also, the value is for indicating how many no operation (NOP) instructions follow a last iteration of the repeated first instruction. The number of repeated instructions plus the number of NOP instructions is equal to the number of pipeline stages in the pipelined processor. In another embodiment, a pipelined data processor is provided for executing the repeating instruction.
Information query