In one embodiment, a system may include a memory unit, a first processing unit configured to write data into a memory region of the memory unit, a second processing unit configured to read data from the memory region, a first control unit configured to control the first processing unit's access to the memory unit and, and a second control unit configured to control the second processing unit's access to the memory unit. The second control unit may be configured to obtain, from the first control unit, a first memory address associated with a data writing process of the first processing unit, receive a read request from the second processing unit, the read request having an associated second memory address, and delay execution of the read request based on a comparison of the first memory address and the second memory address.