Invention Grant
- Patent Title: System and method of timing characterization for semiconductor circuit
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Application No.: US17021702Application Date: 2020-09-15
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Publication No.: US11270052B2Publication Date: 2022-03-08
- Inventor: Chia Hao Tu , Hsueh-Chih Chou , Sang Hoo Dhong , Jerry Chang Jui Kao , Chi-Lin Liu , Cheng-Chung Lin , Shang-Chih Hsieh
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, P.C., Intellectual Property Attorneys
- Agent Anthony King
- Main IPC: G06F30/3312
- IPC: G06F30/3312 ; G06F1/14

Abstract:
A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.
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