A semiconductor memory includes a substrate including a first region in which a plurality of variable resistance elements are arranged, second and third regions on different sides of the first region, a plurality of first lines disposed over the substrate and extending across the first region and the second region, a plurality of second lines disposed over the first lines and extending across the first region and the third region. The variable resistance elements are positioned at intersections of the first lines and the second lines between the first lines and the second lines, a contact plug is disposed in the third region with an upper end coupled to the second line, and a resistive material layer is interposed between the second line and the variable resistance element in the first region but not between the second line and the contact plug in the third region.