Invention Grant
- Patent Title: Reference voltage circuit including depletion type and enhancement type transistors in a common centroid arrangement
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Application No.: US15994075Application Date: 2018-05-31
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Publication No.: US11275399B2Publication Date: 2022-03-15
- Inventor: Masakazu Sugiura , Fumihiko Maetani
- Applicant: ABLIC Inc.
- Applicant Address: JP Chiba
- Assignee: ABLIC Inc.
- Current Assignee: ABLIC Inc.
- Current Assignee Address: JP Chiba
- Agency: Crowell & Moring LLP
- Priority: JPJP2017-109043 20170601
- Main IPC: G05F3/26
- IPC: G05F3/26 ; H01L27/088

Abstract:
There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.
Public/Granted literature
- US20180348807A1 REFERENCE VOLTAGE CIRCUIT AND SEMICONDUCTOR DEVICE Public/Granted day:2018-12-06
Information query
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