Reference voltage circuit including depletion type and enhancement type transistors in a common centroid arrangement
Abstract:
There is provided a reference voltage circuit which includes a depletion type transistor and an enhancement type transistor. At least one of the depletion type transistor and the enhancement type transistor is formed from a plurality of transistors and the reference voltage circuit is arranged in the form of a common centroid (common center of mass) to avoid the influence of a characteristic fluctuation due to stress from the resin encapsulation of a semiconductor device or the like.
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