A data transmission apparatus includes lanes, a first clock generation circuit, a second clock generation circuit, a first circuit, and a second circuit. The first clock generation circuit can generate a first clock as a reference for data transmission in a first lane. The second clock generation circuit can generate a second clock as a reference for data transmission in a second lane. The first circuit can determine a shift amount by notification of a first delay amount of the first lane and a second delay amount of the second lane to cause a delay amount of one of the first clock and the second clock to match a delay amount of the other of the first clock and the second clock. The second circuit can shift the first delay amount or the second delay amount based on the determined shift amount.