- Patent Title: Concurrent optimization of 3D-IC with asymmetrical routing layers
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Application No.: US16789296Application Date: 2020-02-12
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Publication No.: US11276677B1Publication Date: 2022-03-15
- Inventor: Liqun Deng , Pinhong Chen , Richard M. Chou , Chin-Chih Chang , Miao Liu , Yufeng Luo
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F30/394
- IPC: G06F30/394 ; G06F30/398 ; H01L27/02 ; H01L25/065 ; G06F111/04 ; G06F111/00 ; G06F30/39
Abstract:
Disclosed is an approach to implement multi-die concurrent placement, routing, and/or optimization across multiple dies. This permits the multiple dies to be modeled as a single 3D space. Instead of being limited to a 2D plane, a cell can be placed to the area of any of the dies without splitting the netlist beforehand.
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